Many data processing systems require embedded non-volatile memory for storing data for access by other logic components of the data processing system. For example, an integrated circuit may include one or more processing circuits for performing data processing operations, with those data processing circuits being coupled to embedded non-volatile memory for storing data used by those data processing circuits.
However, conventional embedded non-volatile memories such as EEPROM and Flash are expensive, requiring additional mask and process steps during manufacture when compared with the standard complementary metal oxide semiconductor (CMOS) logic process that would be required to produce the other logic components of the integrated circuit. Accordingly, it is necessary to either employ such additional mask and process steps for the entire die of the integrated circuit, or instead to provide the EEPROM or Flash memory off-chip.
However, the article “Embedded Flash Memory for Security Applications in a 0.13 μm CMOS Logic Process”, by J Raszka et al, IEEE International Solid-State Circuits Conference, 2004, describes a non-volatile embedded Flash memory that can be manufactured using a standard CMOS logic process with no special masks or additional process steps. Each of the memory cells of such a Flash memory require a larger area than the conventional Flash memories, and hence will typically be suitable for use in integrated circuits requiring moderate (rather than large) amounts of non-volatile memory. In such embodiments, the fact that the embedded Flash memory can be manufactured using standard CMOS logic processes is highly beneficial, since it will significantly reduce the complexity, and hence the cost, of manufacture.
FIG. 1 schematically illustrates a cross section of a memory cell structure described in the above article. FIG. 2 provides a simplified illustration of the memory cell structure of FIG. 1. As is apparent from FIGS. 1 and 2, this CMOS non-volatile memory cell structure has a floating gate node (FG) 140 where charge is stored, a coupling capacitor 100, a tunnelling capacitor 130, and a PMOS read transistor 120. Both capacitors are made with thick oxide MOS to minimise the leakage throughout the lifetime of the device, and the coupling capacitor 100 is made to have a capacitance approximately ten to twenty times larger than that of the tunnelling capacitor 130, for reasons that will become apparent from discussion of the programming process below. The read transistor 120 is also made as a thick oxide device.
To program the memory cell structure, a relatively high voltage difference of the order of 7 to 8 volts is established between programming terminal B 160 of the tunnelling capacitor 130 and programming terminal T 150 of the coupling capacitor 100. Due to the capacitance difference between the coupling capacitor 100 and the tunnelling capacitor 130, most of the programming bias is applied to the tunnelling capacitor 130, resulting in charge tunnelling taking place through the gate oxide of the tunnelling capacitor 130. This process results in a charge being stored in the floating gate node 140, which is retained after the programming voltages are removed from the programming terminals 150, 160. If the voltage difference required for programming is established by placing the programming terminal 160 at a higher voltage than the programming terminal 150, then a positive charge will be established on the floating gate node 140 during the programming operation, whilst if instead a larger voltage is placed on the programming terminal 150 relative to the programming terminal 160, a negative charge will be established on the floating gate node 140.
After the programming operation has been completed, the charge stored in the floating gate node 140 can be read using the read transistor 120. In one embodiment, this is achieved by placing a potential difference across the transistor 120 between the nodes 170, 180 sufficient to cause the transistor to turn on, whereafter the current passing through the read transistor is sensed in order to detect the charge (and hence voltage) stored at the floating gate node 140.
As mentioned earlier, whilst such a memory cell structure enables the non-volatile memory to be manufactured using standard CMOS manufacturing steps, one disadvantage is that the memory cells are relatively large. A significant factor in this is that the coupling capacitor has to be made quite large in order to produce the required coupling ratio (ratio of the capacitance of the coupling capacitor 100 to the capacitance of the tunnelling capacitor 130) required to enable programming of the memory cell to proceed as outlined above.
It would accordingly be desirable to enable the manufacturing benefits of such a non-volatile memory to be achieved, but with a reduced size for the individual memory cell structures of the memory.